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TI introduces industry’s highest-performance wideband RF phase-locked loops with integrated voltage-controlled oscillators

TI introduces industry’s highest-performance wideband RF phase-locked loops 

Wide frequency range of up to 9.8 GHz and best phase noise performance reduce system complexity

DALLAS, March 2, 2016 - Texas Instruments  today introduced the industry's highest-performance phase-locked loops (PLLs) with integrated voltage-controlled oscillators (VCOs). Delivering the lowest phase-noise performance in the industry, the LMX2582 and LMX2592's single-chip architecture helps designers achieve a level of performance previously possible only through several discrete devices.

These new wideband devices support output frequencies of up to 9.8 GHz, allowing a single device to support various frequency bands in end applications including test and measurement, defense, microwave backhaul, satellite, and wireless communications equipment. For more information about the new PLLs, see www.ti.com/LMX25x2-pr.  

Key features and benefits

  • Best-in-class VCO phase-noise performance: With 1.8-GHz carrier open-loop VCO phase noise of -144.5 dBc/Hz at 1-MHz offset, these devices are the industry's first PLLs with integrated VCO to meet the multicarrier wireless Global System for Mobile (GSM) Communication standard.
  • Superior PLL phase-noise performance: Featuring the industry's lowest normalized PLL noise floor at -231 dBc/Hz and the highest phase-detector frequency of 400 MHz, the devices enable a very low integrated noise of 47 fs RMS jitter. The devices meet the low noise floor requirements for clocking high speed data converters like TI's industry-leading RF sampling ADC12J4000.
  • Expanded frequency range: Eliminating the need for multiple narrowband devices, the LMX2592 supports 20 MHz to 9.8 GHz, and the LMX2582 supports up to 5.5 GHz, allowing designers to use one PLL for a range of wideband system designs.
  • Improved spur performance: The devices' spur-removal technique can eliminate integer boundary spurs (IBS), enabling designers to improve channel density of their designs.
  • Integrated architecture: Low-dropout regulators (LDOs) manage power-supply variations and improve noise immunity. A channel divider lets designers configure up to two differential outputs.

Tools and support to speed design
Engineers can quickly and easily evaluate the performance of the LMX2592 and LMX2582 with evaluation modules (EVMs). The LMX2592EVM and LMX2582EVM are available today for US$299 from the TI store and authorized distributors.

TI's WEBENCH® Clock Architect online design tool simplifies the design process for a designer using the LMX2592 and LMX2582, as well as TI's other clock and timing devices. The tool can recommend a single- or multiple-device clock-tree solution from a broad database of devices. It features PLL loop filter design, phase-noise simulation, and the ability for designers to optimize clock-tree designs for their performance and cost requirements.

Support is available in the TI E2E™ Community Clocks and Timing forum, where engineers can search for solutions, get help, share knowledge and solve problems with fellow engineers and TI experts.

Package, availability and pricing
The LMX2592 and LMX2582 are available today in a 40-pin, 6-mm-by-6-mm quad flat no-leads (QFN) package. For 1,000-unit quantities, the LMX2592 is priced at US$19.00, and the LMX2582 is priced at US$9.00.

Learn more about TI's PLL portfolio

2016030201 / 02.03.2016 / Electronic-components / Texas Instruments /

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